The present invention relates generally to level shifter circuits, and more particularly to a level shifter circuit in a large scale integrated circuit (LSI), having multiple circuit blocks operating at different power supply voltages, the level shifter circuit translating a signal from a lower power supply voltage to a higher power supply voltage.
A large scale integrated circuit (LSI) can include a single integrated circuit (e.g., a chip) having one logic circuit system adapted to operate with a high voltage power source, and another logic circuit system adapted to operate with a low voltage power source. Such an LSI can include a level shifter circuit that operates with the high voltage power source. The level shifter circuit converts an output signal from the lower voltage operating circuit system to a higher level for use in the higher voltage operating circuit system and/or for output via an external pin, or the like.
In an LSI having a number of blocks adapted to operate with different voltage power sources, like that described above, power consumption can be reduced by turning off (powering down) particular voltage power sources when the corresponding blocks are not in operation. Drawbacks can arise in such arrangements when a voltage power source is turned off. In particular, when a lower voltage power source is turned off, input signals for a level shifter circuit can become indeterminate. Such indeterminate input values can result in a leakage current flowing through an inverter within a level shifter circuit. Such a leakage current results in wasteful power consumption.
One conventional approach to addressing the above problem is shown in Japanese Patent Publication 9-74348A (hereinafter JP 9-74348A). JP 9-74348A shows an arrangement in which a level shifter circuit can be placed in an off state when a low voltage power source is turned off. This can prevent a current from flowing through the level shifter circuit when a low voltage power source is in the xe2x80x9cpower-downxe2x80x9d state, thereby reducing power consumption.
FIG. 3 is a schematic diagram of a conventional level shifter circuit having the above-mentioned power down function. In FIG. 3, a terminal 1 can be an input terminal that receives an output signal from a low voltage system circuit. A terminal 2 can be a control terminal that receives a high voltage level when a low voltage power source is on and a ground voltage level when the low power voltage source is off. A terminal 3 can be an output terminal that provides a level shifted output signal. An input signal at a terminal 1 can be received by a level shifter unit 12 directly or through an inverter 10 operating at the low voltage power source. An output signal that is level shifted by a level shifter unit 12 can be supplied to terminal 3 by an inverter 11. An inverter 11 operates at the high voltage power source.
The conventional level shifter unit 12 includes p-channel metal-oxide-semiconductor (PMOS) transistors 4 and 5 and n-channel MOS (NMOS) transistors 7 and 8. PMOS transistors 4 and 5 have source electrodes connected to a high voltage power source and gate electrodes connected in a cross-coupled fashion to their respective drains. NMOS transistors 7 and 8 have gate electrodes that receive an output of inverter 10 and terminal 1, respectively, drain electrodes connected to the drains of PMOS transistors 4 and 5, respectively, and commonly connected source electrodes. A signal obtained by level shifting can be output at the drain electrodes of commonly connected PMOS transistor 5 and NMOS transistor 8.
In order to provide sufficient drive capacity, a channel width of a PMOS transistor 5 connected to an output side of level shifter unit 12 can be larger than that of PMOS transistor 4 connected to an input side of the level shifter unit 12.
The arrangement of FIG. 3 also includes an NMOS transistor 9 having a source-drain path connected between the commonly connected sources of NMOS transistors 7 and 8 and a ground potential. When a low voltage power source is on, a terminal 2 can receive a high voltage level that is applied to a gate of NMOS transistor 9. NMOS transistor 9 can turn on and bring level shifter unit 12 into an operational state. When a low voltage power source is off, a terminal 2 can receive a low voltage level that is applied to a gate of NMOS transistor 9. NMOS transistor 9 can turn off to stop the operation of level shifter unit 12.
In addition, a PMOS transistor 6 can be included that has a source-drain path connected between the output terminal of level shifter unit 12 and a high voltage power source. PMOS transistor 6 can provide a xe2x80x9cpull-upxe2x80x9d operation. As noted above, when the low voltage power source is on, a terminal 2 can receive a high voltage level that is applied to a gate of PMOS transistor 6, and PMOS transistor 6 can be turned off. In contrast, when the low voltage power source is off, a terminal 2 can receive a low voltage level that is applied to a gate of PMOS transistor 6. PMOS transistor 6 can turn on, thereby pulling the output terminal of level shifter 12 to a high voltage level. The operation of inverter 11 can fix the output terminal 3 at a low level.
As has been shown above, the level shifter circuit having the power down function of FIG. 3 includes inverters 10 and 11, level shifter unit 12, NMOS transistor 9 for controlling the operation of the level shifter unit 12, and PMOS transistor 6 for pulling the level of the output terminal of the level shifter unit 12 to a high voltage level when the level shifter unit 12 is in a non-operation state. In this configuration, when a low voltage power source is off, because NMOS transistor 9 is turned off, level shifter unit 12 can be placed in a non-operation state, thereby preventing current from flowing through the level shifter unit 12. In addition, PMOS transistor 6 is turned on, causing the output of level shifter unit 12 to go to a high level, which fixes the level of output terminal 3 at a low level.
As the scale of an LSI increases, the number of terminals that are to be connected to an external circuit can also increase. Consequently, the number of pins required for external connections for an LSI can increase correspondingly. Such increases in pin count can undesirably increase LSI package size, cost, or the like. In order to avoid unduly increasing the pin count of an LSI device, specifications are proposed in which output pins are shared among multiple blocks of an LSI by a mode switching operation. For example, an LSI device may include 224 pins, but 60 such pins are shared.
In devices like that described above, which include multiple blocks operating at different voltage power source levels and shared common output terminals, a level shifter is used in an input/output (I/O) buffer. In addition, it is also desirable to provide power-down modes for such devices. In a power-down mode, a block that does not output a signal to I/O buffer can be turned off.
FIG. 4 is a block schematic diagram showing an example of an LSI configured according to the above specifications.
Referring now to FIG. 4, an LSI 400 can include a low voltage system block 401 adapted to operate with a low voltage power source (e.g., 2.5 volts), a high voltage system block 404 adapted to operate with a high voltage power source (e.g., 3.5 volts), and an I/O buffer 405 that has a level shifter circuit and a signal selector circuit. Output signals from a low voltage system block 401, output signals from a high voltage system block 404, and a power-down mode switching signal from a terminal 402 can be input to I/O buffer 405. I/O buffer 405 can output signals from high voltage system block 404 through terminals 403 when high voltage system block 404 is in operation. I/O buffer 405 can also level shift output signals from low voltage system block 401, and output the resulting level shifted signals through terminals 403 when low voltage system block 401 is in operation.
FIG. 5 is a schematic diagram showing one example of I/O buffer 405 of FIG. 4 that includes the level shifter circuit of FIG. 3. Referring to FIG. 5, a selector circuit 513 can receive a level shifted signal and high voltage signal as inputs. A level shifted signal is generated by a level shifter circuit raising the level of an output signal received from low voltage system block 401, which is adapted to operate with a low voltage power source. A high voltage signal can be an output signal from high voltage system block 404, which is adapted to operate with a high voltage power source.
In response to a control signal (which varies between a high voltage level and a ground level) received at a control terminal 2, the selector circuit 513 selects either the level shifted signal or the high voltage signal, and outputs the selected signal at terminal 503.
FIGS. 6(a) to 6(c) shows an example of a selector circuit 513. FIG. 6(a) shows a complete example of a selector circuit 513. FIG. 6(b) shows an equivalent circuit to that of FIG. 6(a) that corresponds to the application of a high electric potential to control terminal 602 so that a level shifted output signal is selected. FIG. 6(c) shows an equivalent circuit to that of FIG. 6(a) that corresponds to the application of a low (ground) electric potential to control terminal 602 so that a high voltage signal is selected.
Referring to FIG. 6(a), when a high-electric potential signal is supplied to control terminal 602, PMOS transistor 615 and NMOS transistor 618 are turned off, while PMOS transistor 612 and NMOS transistor 613 are turned on. This results in PMOS transistor 616 being essentially short-circuited between its source and drain, and the source electrode of NMOS transistor 617 being isolated from a ground potential.
As result of the above arrangement, a complementary MOS (CMOS) inverter can be formed from PMOS transistor 611 and an NMOS transistor 614. Such a CMOS inverter can invert in phase and amplify a signal received at terminal 601 to provide an output at a common drain connection point of PMOS transistor 611 and NMOS transistor 614. At this time, PMOS transistor 616 and NMOS transistor 617 are placed in a non-operation state by PMOS transistor 612 and NMOS transistor 618, thus a signal from a high voltage system block received at terminal 604 is not output.
In contrast, in a power-down mode, a low electric potential signal is supplied to control terminal 602, PMOS transistor 615 and NMOS transistor 618 are turned on, while PMOS transistor 612 and NMOS transistor 613 are turned off. This results in PMOS transistor 611 being essentially short-circuited between its source and drain, and the drain electrode of NMOS transistor 614 being isolated from an output terminal.
As result of the above arrangement, a CMOS inverter can be formed from PMOS transistor 616 and NMOS transistor 617. Such a CMOS inverter can invert in phase and amplify a signal received at terminal 604 to provide an output at a common drain connection point of PMOS transistor 616 and NMOS transistor 617. At this time, PMOS transistor 611 and NMOS transistor 614 are placed in a non-operation state by PMOS transistor 615 and NMOS transistor 613, thus a level shifted signal from a low voltage system block received at terminal 601 is not output.
FIG. 7 shows another example of an I/O buffer 405. In FIG. 7, a low voltage system inverter 710 can be connected to a non-inverted side of a level shifter unit. A clocked inverter 705 and a clocked inverter 706 can be connected to an output of level shifter unit. Clocked inverter 705 can invert a phase of an output signal of level shifter unit when a signal having a high potential is supplied to control terminal 702. In addition, a clocked inverter 706 can invert a phase of a high voltage output signal when a signal having a low potential is supplied to control terminal 702. A resulting output signal is provided as an input to high voltage system inverter 711.
In the conventional arrangement of FIG. 7, when a signal at a high electric potential is supplied to control terminal 702, a PMOS transistor 715 and an NMOS transistor 716 can be turned on, while a PMOS transistor 719 and an NMOS transistor 720 are turned off. Thus, a clocked inverter 705 can be placed in an operational state, while clocked inverter 706 can be placed in a non-operational state. In such an arrangement, a level-shifted signal, generated by level shifting a low voltage input signal IN, can be output via common output terminal 703. At the same time, a high voltage signal generated from high voltage input signal DATA can be prevented from being output.
In contrast, when a signal at a low potential is supplied to control terminal 702, a PMOS transistor 719 and an NMOS transistor 720 can be turned on, while a PMOS transistor 715 and an NMOS transistor 716 are turned off. Thus, a clocked inverter 706 can be placed in an operational state, while clocked inverter 705 can be placed in a non-operational state. In such an arrangement, a high voltage signal generated from high voltage input signal DATA can be output via common output terminal 703. At the same time, a level-shifted signal, generated by level shifting a low voltage input signal IN, can be prevented from being output.
The various conventional arrangements described above have illustrated circuits that may output signals from different blocks, operating at different power source supplies, at a common output terminal with a switching operation. In particular, in order to maintain driving capacity and to prevent a non-selected signal from interfering with a selected signal, a signal selector circuit is adopted that includes clocked inverters, or the like, that can prevent a non-selected signal from being output. However, as shown in FIGS. 6(a) and 7, such approaches require eight transistors for implementing such clocked inverters. Such a number of transistors can consume considerable circuit area.
Consequently, as the number of common output terminals within an LSI I/O buffer is increased, the resulting number of transistors required increases. Such an increase in the number of transistors increases overall circuit area. Increases in circuit area can translate directly into increases in cost.
In light of the foregoing, it would desirable to arrive at some way of reducing the number of transistors for a signal selector. In particular, it would be desirable to reduce the transistor count for a signal selector that selects an output signal from multiple output signals generated by different blocks, where such blocks operate at different power supply voltages.
It would also be desirable to provide a level shifter circuit suitable for operation with an improved signal selector, like that described above. Such a level shifter circuit can shift an output signal from a circuit system operating at a lower voltage power source, to a higher voltage level.
The present invention may include a level shifter circuit that may be used in a large scale integrated circuit (LSI) having different circuit blocks that operate with different voltage sources. Signals from the different circuit blocks can be output from a common output terminal by a mode switching operation. In an operational state, the level shifter circuit can provide an output signal at a higher voltage level in response to an input signal at a lower voltage level. In a non-operational state, a level shifter unit can set an output to a high impedance state. Such an arrangement can allow an output of a level shifter unit to be connected directly to a clocked inverter that receives an output signal from a block operating at a higher voltage level.
A level shifter circuit according to one embodiment can include an input unit for receiving a first signal that can vary between a first voltage source and a second voltage source and a level shifter unit. A level shifter unit can convert a first signal to a level-shifted signal that varies between the first voltage source and a third voltage source. The level shifter circuit can also include a voltage source cut-off means for isolating the level shifter unit from at least one of the first or third voltage sources, and a high impedance setting means for placing an output terminal of the level shifter unit into a high impedance state when the level shifter unit is isolated from the least one of the first or third voltage sources.
According to one aspect of the embodiments, a level shifter unit can include a first transistor of a first conductivity type having a source electrode coupled to a third voltage source, a second transistor of the first conductivity type having a source electrode coupled to the third voltage source, a gate coupled to a drain of the first transistor, and a drain coupled to gate of the first transistor, a third transistor of a second conductivity type having a drain electrode coupled to the drain electrode of the first transistor, and a gate electrode coupled to receive a first signal, and a fourth transistor of the second conductivity type having a drain electrode coupled to the drain electrode of the second transistor, and a gate electrode coupled to receive the first signal. In one particular approach, a first conductivity type can be p-type and a second conductivity type can be n-type.
According to another aspect of the embodiments, a voltage source cut-off means of a level shifter unit can include a fifth transistor of the second conductivity type having a source-drain path coupled between the source of the third transistor and the first voltage source, and a gate coupled to a control terminal that receives an operation mode control signal, and a sixth transistor of the second conductivity type having a source-drain path coupled between the source of the fourth transistor and the first voltage source and a gate coupled to the control terminal.
According to another aspect of the embodiments, a high impedance setting means can include a fifth transistor of the first conductivity type having a source-drain path connected in parallel with a source-drain path of the first transistor. In one particular arrangement, a fifth transistor can have a gate coupled to a control terminal.
According to another aspect of the embodiments, a high impedance setting means of a level shifter unit can include a fifth transistor of the first conductivity type having a source-drain path connected in series between the source of the second transistor and a third voltage source. In one particular arrangement, a control terminal can be coupled to a gate of the fifth transistor by a control signal inverter.
According to another aspect of the embodiments, a level shifter circuit may further include a first inverter operating between the first voltage source and the second voltage source that provides an inverted first signal to the level shifter unit. The level shifter unit can provide a level-shifted signal that is inverted with respect to the first signal. In addition, a second inverter can be provided that operates between the first voltage source and the third voltage source, and that inverts the level-shifted signal to provide an output signal.
According to another aspect of the embodiments, a level shifter circuit may further include a clocked inverter having a data input that receives a second signal that can vary between the first voltage source and the third voltage source, a clock input coupled to receive control signal, and an output node coupled to an output node of the level shifter unit.
The present invention can also include a semiconductor device that includes a first block that operates with a first voltage source, a second block that operates with a second voltage source, a clocked inverter, and a level shifter circuit. The clocked inverter operates with the second voltage source and receives an output signal from the second block, and includes a clocked inverter output. A level shifter circuit can include a level shifting unit for converting a first signal that operates with the first voltage source into a signal that operates with the second voltage source, as well as a level shifter output coupled to the clocked inverter output. The level shifter circuit also includes a power source cut-off means for cutting off power to the level shifter unit during a power-down mode, and a high impedance setting means for placing an output of the level shifting unit into a high impedance state.
According to one aspect of the embodiments, a level shifter unit can include a first transistor of a first conductivity type having a source electrode coupled to the second voltage source, a second transistor of the first conductivity type having a source electrode coupled to the second voltage source, a gate coupled to a drain of the first transistor, and a drain coupled to gate of the first transistor, a third transistor of a second conductivity type having a drain electrode coupled to the drain electrode of the first transistor, and a gate electrode coupled to receive the first signal, and a fourth transistor of the second conductivity type having a drain electrode coupled to the drain electrode of the second transistor, and a gate electrode coupled to receive the first signal. Further, a power source cut-off means can include a fifth transistor of the second conductivity type having a source-drain path coupled between the source of the third transistor and the first voltage source, and a gate coupled to a control terminal that receives an operation mode control signal, and a sixth transistor of the second conductivity type having a source-drain path coupled between the source of the fourth transistor and the first voltage source and a gate coupled to the control terminal.
According to another aspect of the embodiments, a high impedance setting means can include a sixth transistor of the first conductivity type having a source-drain path connected in parallel with a source-drain path of the first transistor.
According to another aspect of the embodiments, a high impedance setting means can include a sixth transistor of the first conductivity type having a source-drain path connected in series between the source of the second transistor and the third voltage source.
According to another aspect of the embodiments, a clocked inverter can include a seventh transistor of the first conductivity type having a source coupled to the second voltage source and a gate coupled to an output signal from a second block, an eighth transistor of the first conductivity type having source coupled to the drain of the seventh transistor, a drain coupled to an output of the level shifter unit, and a gate coupled to a control signal, a ninth transistor of the second conductivity type having a source coupled to a third voltage source, a gate coupled to the output signal from the second block, and a tenth transistor of the second conductivity type having a source coupled to the drain of the ninth transistor, a drain coupled to the output terminal of the level shifting unit, and a gate coupled to a control terminal.
The present invention may also include a semiconductor device that includes a first circuit block that operates with a first voltage source, a second circuit block that operates with a second voltage source, and a level shifter section. A level shifter section can include a first current path between the second voltage source and a third voltage source having an input coupled to a first signal from the first circuit block, and a second current path between the second voltage source and the third voltage source having an input coupled to the first signal. The second current path can have a low impedance between an output node and the second voltage source in a first mode and a high impedance between the output node and the second voltage source in a second mode.
According to one aspect of the embodiments, a level shifter section can include a second current path having an output transistor with a source drain path coupled between an output node and the second voltage source, and an impedance control transistor having a source drain path coupled between the gate of the output transistor and the second voltage source, and a gate coupled to a control signal.
According to another aspect of the embodiments, a level shifter section can include the level shifter section including a second current path having an output transistor with a source drain path coupled between the output node and the second voltage source, and an impedance control transistor having a source drain path coupled between the source of the output transistor and the second voltage source, and a gate coupled to a control signal.
According to another aspect of the embodiments, a semiconductor device can further include an output inverter having a first output current path coupled between the output node and the second voltage source, the first output current path being disabled in a first mode and enabled in the second mode, and a second output current path coupled between the output node and the third voltage source, the second output current path being disabled in the first mode and enabled in the second mode.
According to another aspect of the embodiments, a level shifter section can include a power source cut-off circuit that provides a low impedance between the third voltage source and the first and second current paths in the first mode and a high impedance between the third voltage source and the first and second current paths in the second mode.